1. Field of the Invention
The present invention relates in general to integrated circuit testers and in particular to an integrated circuit tester formed by multiple, self-synchronizing tester modules.
2. Description of Related Art
A typical integrated circuit (IC) tester performs a digital logic test by stimulating input terminals of an integrated circuit device under test (DUT) with digital logic test signals during a succession of test cycles. The tester monitors the DUT's digital output signals during each test cycle to determine whether they are responding as expected to the stimulus. The typical IC tester includes a set of circuit boards, each including one or more tester channels. At the start of each test cycle, each tester channel receives input control data defining an action or actions to be taken at a DUT terminal during the test cycle. A test action may include changing the state of a test signal at a particular time or times during the test cycle or ascertaining whether the DUT output signal is of a particular state at some particular time during the test cycle. In early testers a large central pattern generator produced input data for each tester channel at the start of each test cycle. The data was delivered concurrently from the pattern generator to all tester boards via a large star bus. However, as the number of DUT terminals increased, the centralized pattern generation architecture became impractical in part because the star bus needed to deliver the data to the tester channels became too large.
IC testers now typically distribute the pattern generation function, with each tester board including its own pattern generator. A typical pattern generator includes a pattern memory storing at each address data that is to be provided to one or more tester channel(s) for a corresponding cycle of the test. At the start of each test cycle a sequencer increments the pattern memory's address so that the pattern memory reads out the control data for that cycle to the tester channel(s). To program the tester boards to carry out a test, a central host computer successively writes the data into the pattern memory of each tester board via a high-speed parallel data bus. The host also writes configuration data into various registers within each board for controlling various test parameters such as, for example, the logic levels employed by the test signals. The host then transmits a START signal concurrently to sequencers in all pattern generators so that they begin addressing the pattern memories concurrently. Thereafter the sequencers, all clocked concurrently by a centralized clock source, synchronize their counts so that all pattern memories read out data for the same test cycle at the same time.
Many integrated circuit testers can perform other types of tests on an integrated circuit. For example, in a leakage current pass/fail test a known voltage is supplied to a DUT terminal through a resistor. A voltage produced across the resistor by current in the DUT terminal is compared to reference voltages to determine whether the current in the DUT terminal is within a specified range. In a parametric leakage current measurement test, a tester measures the actual value of leakage current at a DUT. Often several different types of tests are performed in sequence on a DUT. Before each test of the sequence, the host computer must send new data to the tester boards to reconfigure them for the test. Often the amount of time the host requires to reconfigure all modules before each test of a sequence greatly exceeds the amount of time required to actually perform the test. A high-speed computer bus connection between the host and the modules is needed to reduce overall testing time, particularly when the host must reprogram the modules after each test. To reduce data transmission time between tests, host computers in some testers compress the pattern data before sending it to the various tester boards. In these testers each tester board is provided with processors for decompressing the pattern data either before the test begins or as the test progresses. Since pattern data is often highly compressible, the amount of time the host requires to send data to the circuit boards can be greatly reduced by compressing the data. Nonetheless, the data transmission time between tests can remain a significant portion of the time a tester requires to perform a sequence of tests on a DUT.
A typical large integrated circuit tester includes a test head, a structure that provides the physical contact between tester electronics and the IC. A test head can be mounted on an IC handler, a machine that sequentially delivers ICs to the test head. The tester circuit boards can be mounted on the test head or in a nearby chassis. Because the host computer is connected to the tester boards through a high speed parallel computer bus, and since such a bus must be relatively short, the host computer must be located near the tester boards.
It would be desirable to allow a single host computer to control tester boards of several separate IC testers. However there are several reasons why prior art technology makes this unfeasible. First, since all of the channels of an integrated circuit tester operate synchronously, tests on separate IC's must start at the same time, stop at the same time, and have a similar test period length. Thus it would be difficult to program two groups of tester boards to carry out different tests at the same time. Prior art testers can test more than one DUT at the same time, but all DUTs being tested must be similar and must be tested in the same way. Also since the tester boards must be connected to the host via a short parallel computer bus, it is not practical to separate groups of tester boards so that they can be on or near test heads mounted on separate handlers somewhat distant from one another. The limitation on computer bus length also places a limitation on the number of tester boards that can be connected to the bus.
The demands made on the host by a large IC tester can also make it difficult for the host to control a large number of tester boards. In an integrated circuit tester capable of carrying out more than one type of test on a DUT, the host computer must supply considerable amount of data to each tester board before each test. This activity can keep the host quite busy since the host typically can only configure one board at a time. Bandwidth limitations on the bus connecting the host to the tester boards provide a practical limit to the number of tester boards that the host can reprogram within a reasonable time between tests.
What is needed is a modular integrated circuit tester architecture that allows a single host to control multiple tester modules, wherein modules can operate either independently or in groups to perform differing test sequences on separate sets of integrated circuits, wherein modules may be physically separated from the host by relatively large distances, and wherein the host does not have to reconfigure each module between each test.